1. Field of the Invention
The invention relates generally to a method of forming a triple well of a semiconductor device, and more particularly to a method of forming a triple well of a semiconductor device in which a medium current implanter not a high energy ion implanter and SEG (selective epitaxial growth) process are used to form a triple well, thus preventing a latch-up current path of a parasitic PNPN structure that can create between neighboring n-well and p-well.
2. Description of the Prior Art
FIGS. 1A through 1F are flowcharts to illustrate a conventional method of forming a triple well of a semiconductor device. First, referring to FIG. 1A, a field oxide film 2 is formed at a given region of a silicon wafer 1. Then, as shown in FIG. 1B, ion injection mask process for forming a n-type buried layer is performed using a photoresist 3, and then ion injection process for forming a n-type buried layer 4 is performed using a high energy ion implanter.
Next, as shown in FIG. 1C, after the photoresist 3 is removed, ion injection mask process for forming an n-well is performed again using a photoresist 5. Then, ion injection process for forming an n-well 6 and a p-channel field stop region 7 is performed using a high-energy ion implanter.
Thereafter, as shown in FIG. 1D, after the photoresist 5 is removed, ion injection mask process for forming a p-well is performed again using a photoresist 8. Then, ion injection process for forming a p-well 9 and an n-channel field stop region 10 is performed using a high-energy ion implanter, thus forming a profiled p-well.
Then, as shown FIG. 1E, the photoresist 8 is removed, the formed profiled n-well and p-well are activated by thermal process to form a first p-well 11 and n-well 12, and a second p-well 13, thus completing a triple well forming process.
Next, as shown is FIG. 1F, using a subsequent process, a nMOS is formed at the first p-well 11 and the second p-well 13, and a pMOS is formed at the n-well 12. In particular, an independent transistor, that is different from the transistor formed at the first p-well 11, may be formed at the second p-well 13. As being surrounded by the n-type buried layer, it can be protected from an external voltage or noises that may be introduced.
However, in case of non-volatile memory devices (logic circuits) or higher integrated devices having more than 256 M DRAM, it is required that reduction of the device area must be considered. Thus, it is a trend that the device separation distance is reduced. Therefore, in CMOS device in which the nMOS and pMOS devices are closely located, it is unavoidable that a latch-up phenomenon due to a parasitic PNPN structure occurs.
FIG. 2 is a schematic view to illustrate a latch-up current paten at a CMOS device manufactured by a conventional method. As shown in FIG. 2, a latch-up current path is first generated within a bulk and then is gradually diffused into its surface, thus generating a latch-up phenomenon that is critical to the device operation.
FIG. 3 is a schematic view of a latch-up current path at a STI (shallow trench isolation) structure to which a lot of study has been recently made as a device separation technology in a device with more than 256 M DRAM. In this structure, though some of a latch-up current path is blocked toward the surface, it is unavoidable that a latch-up phenomenon occurs because latch-up current is first generated within its bulk.